GATE CS 2024 Set 2 — Question 61
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Computer Organization & Architecture → Instructions & Addressing Modes → Instruction Formats
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Question
A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.R-type Instruction Format:
I-type Instruction Format:
In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.Let be the number of bits used to encode the UNUSED field, be the number of bits used to encode the OPCODE field, and be the number of bits used to encode the immediate value/address field. The value of is ________
| OPCODE | UNUSED | DST Register | SRC Register1 | SRC Register 2 |
|---|
| OPCODE | DST Register | SRC Register | # Immediate value/address |
|---|
Correct answer
34 to 34
Solution
1.Determine the number of bits for the OPCODE field ():
- Total instructions = 150.
- Instructions are equally divided: 75 R-type and 75 I-type.
- 1 bit is used to distinguish between types (R-type vs I-type).
- To represent 75 distinct operations within each type, we need bits.
- Therefore, total bits for the OPCODE field, bits.
- The processor has 50 architectural registers.
- Bits required to uniquely identify each register = bits.
- All register fields (DST, SRC1, SRC2, SRC) are of equal size, so each is 6 bits.
- Total instruction length = 32 bits.
- R-type format:
- bits.
- I-type format:
- bits.
- .
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