GATE CS 2025 Set 2 — Question 56
Go beyond PYQs with Success TrackerAI-powered personalised practice and doubt support. Unlimited practice on eligible plans; AI usage limits apply.NAT+2 / -0MediumPipeline Stages & ThroughputInstruction PipeliningComputer Organization & Architecture
Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput
Last updated
Question
A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)
Correct answer
260.2 to 261.2
Solution
To find the total time taken to process the instructions in a pipeline, we first determine the clock cycle time ().
Given:
1.Calculate Clock Cycle Time ():
The clock cycle time is determined by the maximum stage delay plus the inter-stage latch delay.2.Calculate Total Execution Time ():
For a -stage pipeline executing instructions, the total number of clock cycles required is .Given:
- Number of stages () = 5
- Number of instructions () = 1000
3.Convert to Microseconds ():
Since :Rounding to two decimal places, the time taken is .Continue learning with Success Tracker
A step still unclear? Work through it with support
Use Success Tracker to ask about the reasoning, then try another GATE CS question to check your understanding.
AI-powered practice· Unlimited practice on eligible plans
- PYQs with solutions
- Attempt available previous-year questions, then compare your reasoning with the worked solution. Coverage varies by stream.
- Practice that adapts
- Choose a topic, work on weaker areas and bookmark questions to revisit. Your attempts feed your progress tracking.
- AI doubt support
- Ask follow-up questions about a step or concept while practising, instead of stopping at the final answer.
Unlimited practice is available on eligible plans. Free practice and AI usage have limits; check the current plan allowances before choosing.
This page stays readable without an account. AI responses can be wrong; check them against the solution and source material.
More questions on Instruction Pipelining
2026 Set 1 Q14Match each addressing mode in List I with a data element or an element of a data structure (in…2026 Set 1 Q15Consider a processor P whose instruction set architecture is the load-store architecture. The…2026 Set 1 Q16Which one of the following dependencies among the register operands of different instructions can…2026 Set 2 Q18Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In…2026 Set 1 Q38The size of the physical address space of a processor is bytes. The capacity of a cache…