GATE CS 2026 Set 1 — Question 60
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stalls
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Question
The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of and (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below.
The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible. When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer)
| Instruction | in nanoseconds | |
|---|---|---|
| LOAD | 1.8 | 15 |
| IMUL | 1.5 | 10 |
| IDIV | 2.5 | 5 |
| FADD | 1.7 | 10 |
| FSUB | 1.7 | 5 |
| FMUL | 2.8 | 15 |
| FDIV | 3.2 | 5 |
| All other instructions | Less than 1.0 | 35 |
Correct answer
95 to 95
Solution
Given:
- Clock cycle time () = 1 ns.
- An instruction with execution time will occupy the EX stage for clock cycles.
- If an instruction occupies the EX stage for cycles, it causes stall cycles for subsequent instructions due to the structural hazard in the EX stage (assuming a single non-pipelined execution unit for the EX stage).
1.LOAD: ns, . Cycles = . Stalls = .
2.IMUL: ns, . Cycles = . Stalls = .
3.IDIV: ns, . Cycles = . Stalls = .
4.FADD: ns, . Cycles = . Stalls = .
5.FSUB: ns, . Cycles = . Stalls = .
6.FMUL: ns, . Cycles = . Stalls = .
7.FDIV: ns, . Cycles = . Stalls = .
8.All other instructions: ns, . Cycles = 1. Stalls = .
Total stall cycles = .Continue learning with Success Tracker
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