GATE CS 2026 Set 2 — Question 57
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stalls
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Question
A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ___________. (rounded off to two decimal places)Note:
Correct answer
2.3 to 2.4
Solution
Speedup () is defined as the ratio of the execution time of the non-pipelined system to the execution time of the pipelined system for the same program.Non-pipelined system:
- Clock frequency, GHz
- Average cycles per instruction,
- Execution time per instruction, seconds.
- Clock frequency, GHz
- Ideal
- 30% of instructions have a 2-cycle stall. Average
- Execution time per instruction, seconds.
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