GATE CS 2014 Set 2 — Question 54
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Computer Organization & Architecture → Memory Hierarchy & Cache → Set-Associative Cache
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Question
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
Correct answer
(D) Width of processor to main memory data bus
Solution
Let Cache Capacity , Block Size , Associativity .
Number of sets .If is doubled to :
Number of sets .If is doubled to :
1.Number of sets becomes . The set index bits decrease by 1. This affects the set index decoder (B).
2.Tag bits = Address bits - Index bits - Offset bits. Since index bits decrease, tag bits increase. This affects the tag comparator width (A).
3.The way selection multiplexor selects one of blocks. If doubles, the multiplexor size/width changes (C).
4.The width of the processor to main memory data bus is an architectural property of the memory system and bus interface, independent of the internal cache organization (associativity). Thus, it is not affected.
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