GATE CS 2014 Set 3 — Question 19
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput
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Question
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.P1: Four-stage pipeline with stage latencies ns, ns, ns, ns.
P2: Four-stage pipeline with stage latencies ns, ns, ns, ns.
P3: Five-stage pipeline with stage latencies ns, ns, ns, ns, ns.
P4: Five-stage pipeline with stage latencies ns, ns, ns, ns, ns.Which processor has the highest peak clock frequency?
P2: Four-stage pipeline with stage latencies ns, ns, ns, ns.
P3: Five-stage pipeline with stage latencies ns, ns, ns, ns, ns.
P4: Five-stage pipeline with stage latencies ns, ns, ns, ns, ns.Which processor has the highest peak clock frequency?
Correct answer
(C) P3
Solution
The clock period of a pipeline is determined by the stage with the maximum latency (bottleneck stage). The peak clock frequency is the inverse of the clock period.Given that pipeline registers have zero latency:
Clock Period () =
Frequency () = For P1:
Stage latencies: ns
ns
GHzFor P2:
Stage latencies: ns
ns
GHzFor P3:
Stage latencies: ns
ns
GHzFor P4:
Stage latencies: ns
ns
GHzComparing the frequencies:
Processor P3 has the highest peak clock frequency.
Clock Period () =
Frequency () = For P1:
Stage latencies: ns
ns
GHzFor P2:
Stage latencies: ns
ns
GHzFor P3:
Stage latencies: ns
ns
GHzFor P4:
Stage latencies: ns
ns
GHzComparing the frequencies:
Processor P3 has the highest peak clock frequency.
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