GATE CS 2015 Set 3 — Question 48
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput
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Question
Consider the following reservation table for a pipeline having three stages and .
The minimum average latency (MAL) is _________.
| 1 | 2 | 3 | 4 | 5 | |
|---|---|---|---|---|---|
| X | X | ||||
| X | X | ||||
| X |
Correct answer
3 to 3
Solution
1.Identify Forbidden Latencies:
- Stage : X at 1 and 5. Distance = .
- Stage : X at 2 and 4. Distance = .
- Stage : X at 3. No distance.
2.Collision Vector:
The maximum forbidden latency is 4. The collision vector has 4 bits ().(latency 4 is forbidden), (latency 2 is forbidden).
.
3.State Diagram:
- Initial State:
- Try shift 1 (latency 1): Allowed since bit 1 is 0.
- Shift right by 1: .
- OR with initial: .
- From state , all latencies 1, 2, 3, 4 are forbidden. Must wait 5 or more cycles.
- Cycle: Average Latency = .
- Try shift 3 (latency 3): Allowed since bit 3 is 0.
- Shift right by 3: .
- OR with initial: .
- From state :
- Bit 1 is 1 (latency 1 forbidden).
- Bit 2 is 1 (latency 2 forbidden).
- Bit 3 is 0 (latency 3 allowed).
- Bit 4 is 1 (latency 4 forbidden).
- Try shift 3 again: Shift right by 3 . OR with initial .
- This forms a greedy cycle: Average Latency = 3.
The maximum number of X's in any single row is 2 (in and ). Thus, MAL .
However, no cycle with average latency < 3 exists.Therefore, the Minimum Average Latency (MAL) is 3.
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