GATE CS 2017 Set 1 — Question 51
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Question
Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)is repeated 10 times. The number of conflict misses experienced by the cache is ________.
Correct answer
76 to 76
Solution
Cache parameters:
Total blocks = 256.
Associativity = 2-way.
Number of sets = sets.
Mapping function: Set index = Block Address .The sequence contains two distinct groups of addresses:
Group 1: 0, 128, 256. All map to Set .
Group 2: 1, 129, 257. All map to Set .Since the sets are independent, we calculate misses for Set 0 and multiply by 2 (as the pattern for Set 1 is identical).Analysis for Set 0 (Capacity 2 blocks, LRU):
Sequence per iteration: 0, 128, 256, 128, 0, 128, 256, 128.Iteration 1:
State at end of Iteration 1: Cache contains {128, 256}, LRU is 256.Iteration 2 (and subsequent 3-10):
Start state: {128, 256}, LRU: 256.
Iteration 1: 2 conflict misses.
Iterations 2 to 10 (9 iterations): conflict misses.
Total for Set 0 = .Total Conflict Misses for Set 1:
Identical pattern. Total = 38.Grand Total:
.
Total blocks = 256.
Associativity = 2-way.
Number of sets = sets.
Mapping function: Set index = Block Address .The sequence contains two distinct groups of addresses:
Group 1: 0, 128, 256. All map to Set .
Group 2: 1, 129, 257. All map to Set .Since the sets are independent, we calculate misses for Set 0 and multiply by 2 (as the pattern for Set 1 is identical).Analysis for Set 0 (Capacity 2 blocks, LRU):
Sequence per iteration: 0, 128, 256, 128, 0, 128, 256, 128.Iteration 1:
1.Access 0: Miss (Compulsory). Cache: {0}. LRU: 0.
2.Access 128: Miss (Compulsory). Cache: {0, 128}. LRU: 0.
3.Access 256: Miss (Compulsory). Set full, evict LRU (0). Cache: {128, 256}. LRU: 128.
4.Access 128: Hit. Cache: {256, 128}. LRU: 256.
5.Access 0: Miss (Conflict). Evict LRU (256). Cache: {128, 0}. LRU: 128.
6.Access 128: Hit. Cache: {0, 128}. LRU: 0.
7.Access 256: Miss (Conflict). Evict LRU (0). Cache: {128, 256}. LRU: 128.
8.Access 128: Hit. Cache: {256, 128}. LRU: 256.
Misses in Iteration 1: 3 Compulsory, 2 Conflict.State at end of Iteration 1: Cache contains {128, 256}, LRU is 256.Iteration 2 (and subsequent 3-10):
Start state: {128, 256}, LRU: 256.
1.Access 0: Miss (Conflict). Evict 256. Cache: {128, 0}. LRU: 128.
2.Access 128: Hit. Cache: {0, 128}. LRU: 0.
3.Access 256: Miss (Conflict). Evict 0. Cache: {128, 256}. LRU: 128.
4.Access 128: Hit. Cache: {256, 128}. LRU: 256.
5.Access 0: Miss (Conflict). Evict 256. Cache: {128, 0}. LRU: 128.
6.Access 128: Hit. Cache: {0, 128}. LRU: 0.
7.Access 256: Miss (Conflict). Evict 0. Cache: {128, 256}. LRU: 128.
8.Access 128: Hit. Cache: {256, 128}. LRU: 256.
Misses in Iteration (): 0 Compulsory, 4 Conflict.Total Conflict Misses for Set 0:Iteration 1: 2 conflict misses.
Iterations 2 to 10 (9 iterations): conflict misses.
Total for Set 0 = .Total Conflict Misses for Set 1:
Identical pattern. Total = 38.Grand Total:
.
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