GATE CS 2017 Set 1 — Question 50
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput
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Question
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:
(i) a naive pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is ________.
(i) a naive pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is ________.
Correct answer
1.49 to 1.52
Solution
For the Naive Pipeline (NP):
Number of stages .
Stage delays: 5, 4, 20, 10, 3 ns.
Buffer delay: 2 ns.
Clock cycle time ns.
Number of instructions .
Time taken by NP to execute 20 instructions:
ns.For the Efficient Pipeline (EP):
The OF stage (20 ns) is split into OF1 (12 ns) and OF2 (8 ns).
New stages: IF(5), ID(4), OF1(12), OF2(8), EX(10), WB(3).
Number of stages .
Clock cycle time ns.
Time taken by EP to execute 20 instructions:
ns.Speedup .
Rounding to two decimal places, the speedup is .
Number of stages .
Stage delays: 5, 4, 20, 10, 3 ns.
Buffer delay: 2 ns.
Clock cycle time ns.
Number of instructions .
Time taken by NP to execute 20 instructions:
ns.For the Efficient Pipeline (EP):
The OF stage (20 ns) is split into OF1 (12 ns) and OF2 (8 ns).
New stages: IF(5), ID(4), OF1(12), OF2(8), EX(10), WB(3).
Number of stages .
Clock cycle time ns.
Time taken by EP to execute 20 instructions:
ns.Speedup .
Rounding to two decimal places, the speedup is .
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