GATE CS 2021 Set 1 — Question 63
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Computer Organization & Architecture → Instruction Pipelining → Pipeline Stages & Throughput
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Question
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ___________ nanoseconds.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ___________ nanoseconds.
Correct answer
17160 to 17160
Solution
The clock cycle time () is determined by the slowest stage plus the register delay.
Maximum stage delay = ns.
Register delay = ns.
ns.For a -stage pipeline executing instructions without stalls, the total time is given by:
Given and :
ns.
Maximum stage delay = ns.
Register delay = ns.
ns.For a -stage pipeline executing instructions without stalls, the total time is given by:
Given and :
ns.
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